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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2004 analog devices, inc. all rights reserved. ad5426/ad5432/ad5443 * 8-/10-/12-bit high bandwidth multiplying dacs with serial interface features 3.0 v to 5.5 v supply operation 50 mhz serial interface 10 mhz multiplying bandwidth 10 v reference input low glitch energy < 2 nv-s extended temperature range ?0 c to +125 c 10-lead msop package pin compatible 8-, 10-, and 12-bit current output dacs guaranteed monotonic 4-quadrant multiplication power-on reset with brownout detection daisy-chain mode readback function 0.4 a typical power consumption applications portable battery-powered applications waveform generators analog processing instrumentation applications programmable amplifiers and attenuators digitally controlled calibration programmable filters and oscillators composite video ultrasound gain, offset, and voltage trimming general description the ad5426/ad5432/ad5443 are cmos 8-, 10-, and 12-bit current output digital-to-analog converters, respectively. these devices operate from a 3.0 v to 5.5 v power supply, making them suited to battery-powered applications and many other applications. these dacs utilize double buffered 3-wire serial interface that is compatible with spi , qspi , microwire , and most dsp interface standards. in addition, a serial data out pin (sdo) allows for daisy-chaining when multiple packages are used. data readback allows the user to read the contents of the dac register via the sdo pin. on power-up, the internal shift register and latches are filled with 0s and the dac outputs are at zero scale. as a result of manufacture on a cmos submicron process, they offer excellent 4-quadrant multiplication characteristics, with large signal multiplying bandwidths of 10 mhz. functional block diagram control logic and input shift register sclk s ync ad5426/ ad5432/ ad5443 v ref i out 2 r fb r 8-/10-/12-bit r-2r dac dac register sdin input latch v dd gnd sdo power-on reset i out 1 * u.s. patent no. 5,689,257 the applied external reference input voltage (v ref ) determines the full-scale output current. an integrated feedback resistor (r fb ) provides temperature tracking and full-scale voltage output when combined with an external current to voltage precision amplifier. the ad5426/ad5432/ad5443 dacs are available in small 10-lead msop packages.
rev. 0 e2e ad5426/ad5432/ad5443especifications 1 (v dd = 3 v to 5.5 v, v ref = 10 v, i out x = o v. all specifications t min to t max , unless otherwise noted. dc performance measured with op177, ac performance with ad8038, unless otherwise noted.) parameter min typ max unit conditions static performance ad5426 resolution 8 bits relative accuracy + = = = ? = ? = a input capacitance 4 10 pf v dd = 4.5 v to 5.5 v output low voltage, v ol 0.4 v i sink = 200 a output high voltage, v oh v dd e 1 v i source = 200 a v dd = 3 v to 3.6 v output low voltage, v ol 0.4 v i sink = 200 a output high voltage, v oh v dd e 0.5 v i source = 200 a dynamic performance 2 reference multiplying bandwidth 10 mhz v ref = = = ? = = = ? = = sync h e hz hchz hz ns hz hz
rev. 0 ad5426/ad5432/ad5443 e3e parameter min typ max unit conditions sfdr performance (wide band) ad5443, 4096 codes v ref = 3.5 v clock = 10 mhz 50 khz f out 75 db 20 khz f out 76 db sfdr performance (narrow band) clock = 1 mhz 50 khz f out 87 db 20 khz f out 87 db intermodulation distortion clock = 1 mhz f 1 = 20 khz, f 2 = 25 khz 78 db power requirements power supply range 3.0 5.5 v i dd 0.4 5 a logic inputs = 0 v or v dd 0.6 at a = 25 = +
rev. 0 e4e ad5426/ad5432/ad5443 timing characteristics 1 parameter 3.0 v to 5.5 v 4.5 v to 5.5 v unit conditions/comments f sclk 50 50 mhz max max clock frequency t 1 20 20 ns min sclk cycle time t 2 88 ns min sclk high time t 3 88 ns min sclk low time t 4 2 13 13 ns min sync scl sync scl sync scls x nes s y + = = ( ) ( + ) ( = = = ) () () (+) (+) () ()
rev. 0 ad5426/ad5432/ad5443 e5e absolute maximum ratings 1, 2 (t a = 25 ) + + + + ( ) + + ( ) ( ) sync in i l i h c l p pin hin l lcss cin ese es es einie inl p p ls y + + + + + + + + +
rev. 0 e6e ad5426/ad5432/ad5443 pin configuration i out 1 110 r fb sdin 56 sync sclk 47 sdo gnd 38 v dd i out 2 29 v ref ad5426/ ad5432/ ad5443 (not to scale) pin function descriptions pin no. mnemonic function 1i out 1 dac current output. 2i out 2 dac analog ground. this pin should normally be tied to the analog ground of the system. 3g nd ground pin. 4 sclk serial clock input. by default, data is clocked into the input shift register on the falling edge of the serial clock input. alternatively, by means of the serial control bits, the device may be configured such that data is clocked into the shift register on the rising edge of sclk. 5s din serial data input. data is clocked into the 16-bit input register on the active edge of the serial clock input. by default, on power-up, data is clocked into the shift register on the falling edge of sclk. the control bits allow the user to change the active edge to rising edge. 6 sync lciz sync sclin i s s sscl cs ppsi e ci cecx
rev. 0 t ypical performance characteristicsead5426/ad5432/ad5443 e7e code inl (lsb) 0.20 0.10 0.15 0 ?0.05 0.05 ?0.10 ?0.15 ?0.20 050 100 150 250 200 t a = 25 c v ref = 10v v dd = 5v tpc 1. inl vs. code (8-bit dac) code dnl (lsb) 0.20 0.15 0.10 0.05 ?0.10 ?0.05 0 ?0.15 ?0.20 0 200 t a = 25 c v ref = 10v v dd = 5v 50 100 150 250 tpc 4. dnl vs. code (8-bit dac) reference voltage inl (lsb) 0.6 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 2345678910 max inl min inl t a = 25 c v ref = 10v v dd = 5v ad5443 tpc 7. inl vs. reference voltage code inl (lsb) 0.5 0.4 0.3 0.2 0.1 0 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 200 400 800 600 1000 t a = 25 c v ref = 10v v dd = 5v tpc 2. inl vs. code (10-bit dac) code dnl (lsb) 0.5 0.4 0.3 0.1 0.2 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 0 200 400 800 600 1000 t a = 25 c v ref = 10v v dd = 5v tpc 5. dnl vs. code (10-bit dac) reference voltage dnl (lsb) ?0.40 ?0.45 ?0.50 ?0.55 ?0.60 ?0.65 ?0.70 2345678910 min dnl t a = 25 c v ref = 10v v dd = 5v ad5443 tpc 8. dnl vs. reference voltage code inl (lsb) 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4000 t a = 25 c v ref = 10v v dd = 5v tpc 3. inl vs. code (12-bit dac) code dnl (lsb) 1.0 0.2 0.8 0.6 0.4 ?0.2 ?0.4 ?0.6 0 ?0.8 ?1.0 0 500 1000 2000 2500 3000 3500 1500 4000 t a = 25 c v ref = 10v v dd = 5v tpc 6. dnl vs. code (12-bit dac) temperature ( c) error (mv) 5 4 ?3 ?4 0 ?2 3 2 ?5 ?60 ?40 ?20 0 20 40 60 80 100 120 140 ?1 1 v dd = 5v v dd = 3v v ref = 10v tpc 9. gain error vs. temperature
rev. 0 e8e ad5426/ad5432/ad5443 v bias (v) lsb 2.0 1.5 ?1.0 ?1.5 0 ?0.5 1.0 0.5 ?2.0 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 t a = 25 c v ref = 0v v dd = 3v ad5443 max inl min inl max dnl min dnl tpc 10. linearity vs. v bias voltage applied to i out2 t a = 25 c v ref = 2.5v v dd = 3v and 5v gain error offset error voltage (mv) 0.5 ?0.2 ?0.3 ?0.4 0.1 0 0.3 0.4 0.2 ?0.1 ?0.5 v bias (v) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 tpc 13. gain and offset errors vs. v bias voltage applied to i out2 input voltage (v) current (ma) 0.7 0.6 0 0.5 0.4 0.3 5 4 3 2 1 0 0.2 0.1 v dd = 3v v dd = 5v t a = 25 c tpc 16. supply current vs. logic input voltage, sync sc s s c n nn n nn c s s s c n nn n nn c s c c c s s n c n c s s s c n nn n nn c s cn c c c sc
rev. 0 ad5426/ad5432/ad5443 e9e frequency (hz) i dd (a) 3.5 0 100m 3.0 2.0 1.5 1.0 0.5 2.5 10m 1m 100k 10k 1k 100 10 1 t a = 25 c ad5443 loading 010101010101 v cc = 5v v cc = 3v tpc 19. supply current vs. update rate ?9.00 ?6.00 ?3.00 0.00 3.00 10k 100k 1m 10m 100m frequency (hz) t a = 25 c v dd = 5v ad8038 amplifier v ref = 2v, ad8038 c c 1.47pf v ref = 2v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1.47pf v ref = 3.51v, ad8038 c c 1.8pf gain (db) tpc 22. reference multiplying bandwidth vs. frequency and compensation capacitor ?120 ?100 ?80 ?60 0 20 11 0 100 1k 10k 100k 1m 10m frequency (hz) ?40 ?20 t a = 25 c v dd = 3v amp = ad8038 full scale zero scale psrr (db) tpc 25. power supply rejection vs. frequency ?102 ?66 ?54 ?42 ?30 ?18 ?6 6 11 0 100 1k 10k 100k 1m 10m 100m frequency (hz) gain (db) t a = 25 c loading zs to fs 0 ?60 ?48 ?36 ?24 ?12 ?84 ?72 ?78 ?90 ?96 t a = 25 c v dd = 5v v ref = 3.5v input c comp = 1.8pf ad8038 amplifier all on db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 all off tpc 20. reference multiplying bandwidth vs. frequency and code time (ns) output voltage (v) 0.060 ?0.020 0.050 0.020 0.010 0.000 ?0.010 0.040 0.030 300 250 200 150 100 50 0 t a = 25 c v ref = 0v ad8038 amp c comp = 1.8pf ad5443 v dd 3v, 0v ref nrg = 0.088nvs 800h to 7ffh v dd 5v, 0v ref nrg = 0.119nvs, 800h to 7ffh v dd 3v, 0v ref nrg = 1.877nvs 7ffh to 800h v dd 5v, 0v ref nrg = 2.049nvs 7ffh to 800h tpc 23. midscale transition v ref = 0 v ?90 ?85 ?80 ?65 ?60 11 0 100 1k 10k 100k 1m frequency (hz) ?75 ?70 t a = 25 c v dd = 3v v ref = 3.5v p-p thd + n (db) tpc 26. thd and noise vs. frequency ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 11 0 100 1k 10k 100k 1m 100m frequency (hz) t a = 25 c v dd = 5v v ref = 3.5v c comp = 1.8pf ad8038 amplifier 10m gain (db) tpc 21. reference multiplying bandwidth?all ones loaded time (ns) output voltage (v) ?1.700 ?1.760 300 ?1.710 ?1.720 ?1.730 ?1.740 ?1.750 250 200 150 100 50 0 t a = 25 c v ref = 3.5v ad8038 amp c comp = 1.8pf ad5443 v dd 3v, 3.5v ref nrg = 0.647nvs 800h to 7ffh v dd 5v, 3.5v ref, nrg = 0.364nvs, 800h to 7ffh v dd 3v, 3.5v ref nrg = 1.433nvs 7ffh to 800h v dd 5v, 3.5v ref nrg = 1.184nvs 7ffh to 800h tpc 24. midscale transition v ref = 3.5 v temperature ( c) current ( a) 0.7 0 120 0.6 0.4 0.3 0.2 0.1 0.5 100 80 60 40 20 0 ?20 ?40 v dd = 5v v dd = 3v all 1s all 0s tpc 27. supply current vs. temperature
rev. 0 e10e ad5426/ad5432/ad5443 voltage (v) 5.5 threshold voltage (v) 1.8 1.6 0 0.8 0.6 0.4 0.2 1.4 1.0 1.2 5.0 4.5 4.0 3.5 3.0 2.5 t a = 25 c v il v ih tpc 28. threshold voltages vs. supply voltage frequency (hz) sfdr (db) 0 ?70 ?100 50 0 ?10 ?60 ?80 ?90 ?40 ?50 ?20 ?30 100 150 200 250 300 350 400 450 500 t a = 25 c v ref = 3.5v ad8038 amp ad5443 tpc 31. wideband sfdr f out = 50 khz, update = 1 mhz frequency (hz) sfdr (db) 0 ?70 ?100 12 10 ?10 ?60 ?80 ?90 ?40 ?50 ?20 ?30 14 16 18 20 22 24 26 28 30 t a = 25 c v ref = 3.5v ad8038 amp ad5443 tpc 34. narrowband ( ) = = () () = = = = = () () () = = = = () = = ( ) = = () () = = = = = () () () = = ( ) = =
rev. 0 ad5426/ad5432/ad5443 e11e terminology relative accuracy relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for 0 and full scale and is normally expressed in lsbs or as a percentage of full-scale reading. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of e1 lsb max over the operating temperature range ensures monotonicity. gain error gain error or full-scale error is a measure of the output error between an ideal dac and the actual device output. for these dacs, ideal maximum output is v ref e 1 lsb. gain error of the dacs is adjustable to 0 with external resistance. output leakage current output leakage current is current that flows in the dac ladder switches when these are turned off. for the i out 1 terminal, it can be measured by loading all 0s to the dac and measuring the i out 1 current. minimum current will flow in the i out 2 line when the dac is loaded with all 1s. output capacitance capacitance from i out 1 or i out 2 to agnd. output current settling time this is the amount of time it takes for the output to settle to a specified level for a full scale input change. for these devices, it is specified with a 100 ? sync i i e c ci c hh c c h thd vvvv v = +++ () () () ( )
rev. 0 e12e ad5426/ad5432/ad5443 dac section the ad5426, ad5432, and ad5443 are 8-, 10-, and 12-bit cur- rent output dacs consisting of a standard inverting r-2r ladder configuration. a simplified diagram for the 8-bit ad54246 is shown in figure 4. the feedback resistor r fb has a value of r. the value of r is typically 10 k ? ( ? ? ) ( ) sync scl in sync cccc ccc cic z ci c x c z c i cc c c c c i n p l i cse c c c c ls s is c c c c cnlis isc ls s is c c c c cnlis isc ls s is c c c c cnlis isc
rev. 0 ad5426/ad5432/ad5443 e13e sync sync z sync sync sync scl c i sclscl sync i s scl x in x nn s sync x sync sync c n c sc s sync sync scl c sync cicipein vv d out ref n = d is the fractional representation of the digital word loaded to the dac, and n is the number of bits. d= 0 to 255 (8-bit ad5426) = 0 to 1023 (10-bit ad5432) = 0 to 4095 (12-bit ad5443) note that the output voltage polarity is opposite to the v ref polarity for dc reference voltages. these dacs are designed to operate with either negative or positive reference voltages. the v dd power pin is used by only the internal digital logic to drive the dac switches? on and off states. these dacs are also designed to accommodate ac reference input signals in the range of e10 v to +10 v. v out = 0 to ?v ref sclk sdin gnd v ref sync i out 2 i out 1 r fb microcontroller agnd ad5426/ ad5432/ad5443 notes 1. r1 and r2 used only if gain adjustment is required. 2. c1 phase compensation (1pf ? 2pf) may be required if a1 is a high speed amplifier. r1 r2 a1 v ref v dd v dd c1 figure 6. unipolar operation with a fixed 10 v reference, the circuit shown in figure 6 will give a unipolar 0 v to e10 v output voltage swing. when v in is an ac signal, the circuit performs 2-quadrant multiplication. table ii shows the relationship between digital code and expected output voltage for unipolar operation (ad5426, 8-bit device). table ii. unipolar code table digital input analog output (v) 1111 1111 ev ref (255/256) 1000 0000 ev ref (128/256) = ev ref /2 0000 0001 ev ref (1/256) 0000 0000 ev ref (0/256) = 0 bipolar operation in some applications, it may be necessary to generate full 4-quadrant multiplying operation or a bipolar output swing. this can be easily accomplished by using another external amplifier and some external resistors as shown in figure 7. in this circuit, the second amplifier a2 provides a gain of 2. bias- ing the external amplifier with an offset from the reference voltage results in full 4-quadrant multiplying operation. the transfer function of this circuit shows that both negative and positive output voltages are created as the input data (d) is incremented from code zero (v out = ev ref ) to midscale (v out = 0 v ) to full scale (v out = +v ref ). vv d v out ref n ref = ? ? ? ? ? ? d is the fractional representation of the digital word loaded to the dac and n is the resolution of the dac. d= 0 to 255 (8-bit ad5426) = 0 to 1023 (10-bit ad5432) = 0 to 4095 (12-bit ad5443) when v in is an ac signal, the circuit performs 4-quadrant multiplication.
rev. 0 e14e ad5426/ad5432/ad5443 table iii shows the relationship between digital code and the expected output voltage for bipolar operation (ad5426, 8-bit device). table iii. bipolar code table digital input analog output (v) 1111 1111 +v ref (127/128) 1000 0000 0 0000 0001 ev ref (127/128) 0000 0000 ev ref (128/128) stability in the i-to-v configuration, the i out of the dac and the invert- ing node of the op amp must be connected as close as possible, and proper pcb layout techniques must be employed. since every code change corresponds to a step function, gain peaking may occur if the op amp has limited gbp and there is excessive parasitic capacitance at the inverting node. this parasitic capaci- tance introduces a pole into the open-loop response which can cause ringing or instability in closed-loop applications. an optional compensation capacitor, c1 can be added in parallel with r fb for stability as shown in figures 6 and 7. too small a value of c1 can produce ringing at the output, while too large a value can adversely affect the settling time. c1 should be found e mpirically but 1 pf to 2 pf is generally adequate for com pensation. single-supply applications current mode operation these dacs are specified and tested to guarantee operation in single-supply applications. figure 8 shows a typical circuit for operation with a single 3.0 v to 5 v supply. in the current mode circuit of figure 8, i out 2 and hence i out 1 is biased positive by an amount applied to v bias . v out v dd gnd v in i out 2 i out 1 r fb v dd v ref v bias c1 notes 1. additional pins omitted for clarity 2. c1 phase compensation (1pf? 2pf) may be required if a1 is a high speed amplifier. a2 a1 figure 8. single-supply current mode operation in this configuration, the output voltage is given by vdrrvvv out fb dac bias in bias = () ? () {} + () () () vv to v v v out bias out bias in ==? = + ? = () ? ? ?
rev. 0 ad5426/ad5432/ad5443 e15e voltage switching mode of operation figure 9 shows these dacs operating in the voltage-switching mode. the reference voltage, v in , is applied to the i out 1 pin, i out 2 is connected to agnd, and the output voltage is available at the v ref terminal. in this configuration, a positive reference voltage results in a positive output voltage making single-supply operation possible. the output from the dac is voltage at a constant impedance (the dac ladder resistance), thus an op amp is necessary to buffer the output voltage. the reference input no longer sees a constant input impedance, but one that varies with code. so, the voltage input should be driven from a low impedance source. v out v dd gnd v in i out 2 i out 1 r fb v dd v ref notes 1. additional pins omitted for clarity 2. c1 phase compensation (1pf? 2pf) may be required if a1 is a high speed amplifier. r2 r1 a1 figure 9. single-supply voltage switching mode operation also, v in must not go negative by more than 0.3 v or an internal diode will turn on, exceeding the max ratings of the device. in this type of application, the full range of multiplying capability of the dac is lost. positive output voltage note that the output voltage polarity is opposite to the v ref polarity for dc reference voltages. to achieve a positive voltage output, an applied negative reference to the input of the dac is preferred over the output inversion through an inverting amplifier because of the resistor tolerance errors. to generate a negative reference, the reference can be level shifted by an op amp such that the v out and gnd pins of the reference become the virtual ground and e2.5 v, respectively, as shown in figure 10. v out = 0 to +2.5v v dd = 5v gnd i out 2 i out 1 r fb v dd v ref c1 notes 1. additional pins omitted for clarity 2. c1 phase compensation (1pf? 2pf) may be required if a1 is a high speed amplifier. gnd v in v out adr03 + 5v ?5v 1/2 ad8552 1/2 ad8552 ?2.5v a2 a1 figure 10. positive voltage output with minimum of components adding gain in applications where the output voltage is required to be greater t han v in , gain can be added with an additional external amplifier or it can also be achieved in a single stage. it is important to consider the effect of temperature coefficients of the thin film resistors of the dac. simply placing a resistor in series with the r fb resistor will causing mismatches in the temperature coefficients, resulting in larger gain temperature coefficient errors. instead, the circuit of figure 11 is a recommended method of increasing the gain of the circuit. r1, r2, and r3 should all have similar temper- ature coefficients, but they need not match the temperature coefficients of the dac. this approach is recommended in circuits where gains of great than 1 are required. v out v dd gnd i out 2 i out 1 r fb v dd v ref c1 notes 1. additional pins omitted for clarity 2. c1 phase compensation (1pf? 2pf) may be required if a1 is a high speed amplifier. r 3 r 2 r2 v in r1 = r2r3 r2 + r3 gain = r2 + r3 r2 a1 figure 11. increasing gain of current output dac used as a divider or programmable gain element current steering dacs are very flexible and lend themselves to many different applications. if this type of dac is connected as the feedback element of an op amp and r fb is used as the input resistor as shown in figure 12, then the output voltage is inversely proportional to the digital input fraction d. for d = 1e2 n the output voltage is vvdv out in in n =? =? ? () ? () v in . however, if the dac has a linearity specification of +
rev. 0 e16e ad5426/ad5432/ad5443 dac leakage current is also a potential error source in divider circuits. the leakage current must be counterbalanced by an opposite current supplied from the op amp through the dac. since only a fraction d of the current into the v ref terminal is routed to the i out 1 terminal, the output voltage has to change as follows: output error voltage due to dac leakage = (leakage r)/d where r is the dac resistance at the v ref terminal. for a dac leakage current of 10 na, r = 10 k ? ( ) ( ) system drift with temperature should be less than 78 ppm/ ( ) ( ) ( ) ( ) v p-p sc70, tsot, soic adr02 5 v 0.1% 3 ppm/ v p-p sc70, tsot, soic adr03 2.5 v 0.2% 3 ppm/ v p-p sc70, tsot, soic adr425 5 v 0.04% 3 ppm/ v p-p msop, soic table v. some precision adi op amps suitable for use with ad5426/ad5432/ad5443 dacs part no. max supply voltage (v) v os (max) ( v) i b (max) (na) gbp (mhz) slew rate (v/ s) op97 + () () () () ( ) ( ) ()
rev. 0 ad5426/ad5432/ad5443 e17e most single-supply circuits include ground as part of the analog signal range, which in turns requires an amplifier that can handle rail-to-rail signals, there is a large range of single-supply amplifiers available from analog devices. microprocessor interfacing microprocessor interfacing to this family of dacs is via a serial bus that uses standard protocol compatible with microcontrollers and dsp processors. the communications channel is a 3-wire interface consisting of a clock signal, a data signal, and a synchronization signal. the ad5426/ad5432/ad5443 requires a 16-bit word with the default being data valid on the falling edge of sclk, but this is changeable via the control bits in the data-word. adsp-21xx to ad5426/ad5432/ad5443 interface the adsp-21xx family of dsps are easily interface to this family of dacs without extra glue logic. figure 13 shows an example of an spi interface between the dac and the adsp-2191m. sck of the dsp drives the serial data line, din. sync spixsel scl sc sync spixsel sin si sp iinlpinsiecliy spspi i cspsp ixsp c xsp i spc scl c sync scl scl sync s sin sp sp sp iinlpinsiecliy spspspsp i c sclcx sync scl cspxx sp sp s insls ype isclisc se isis slen cli c xsclc x in p sync p cl cp x x cp ls sc s scl x sync p sin x iinlpinsiecliy cl i
rev. 0 e18e ad5426/ad5432/ad5443 mc68hc11 interface to ad5426/ad5432/ad5443 interface figure 16 shows an example of a serial interface between the dac and the mc68hc11 microcontroller. the serial peripheral interface (spi) on the mc68hc11 is configured for master mode (mstr = 1), clock polarity bit (cpol) = 0, and the clock phase bit (cpha) = 1. the spi is configured by writing to the spi control register (spcr)?see the 68hc11 user manual. s ck of the 68hc11 drives the sclk of the dac interface, the mosi output drives the serial data line (d in ) of the ad5516. the sync pc sync pcsi scshc sc pc cpc i sis chc sync scl scl sc sync pc sin si chc iinlpinsiecliy hcl i iciei c icies s cs cscl scl s icie sync cs sin s iinlpinsiecliy icie i piccxx piccxxssp spicp sspcnspici xi sync c scl scc piccxx sync sin si c iinlpinsiecliy piccxx i pclynpespplyecplin i ic nn c f in parallel with 0.1 f on the supply located as close to the pack- age as possible, ideally right up against the device. the 0.1 f capacitor should have low effective series resistance (esr) and effective series inductance (esi), such as the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. low esr 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a micros- trip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. it is good practice to employ compact, minimum lead length pcb layout design. leads to the input should be as short as possible to minimize ir drops and stray inductance. the pcb metal traces between v ref and r fb should also be matched to minimize gain error. to maximize on high frequency performance, the i-to-v amplifier should be located as close to the device as possible.
rev. 0 ad5426/ad5432/ad5443 e19e v dd v ss v out p1?13 p1?5 p1?4 p1?2 p1?3 p1?19 p1?20 p1?21 p1?22 p1?23 p1?24 p1?25 p1?26 p1?27 p1?28 p1?29 p1?30 sclk sdin sync ldac sclk sdin sync sdo/ ldac sclk sdin sync sdo/ ldac sdo gnd i out 2 v dd r fb v ref v ref v dd1 v ref v dd +v in v out trim gnd i out 1 ad5426/ ad5432/ ad5443 u1 u3 c6 4.7pf c1 0.1 f c2 10 f c7 10 f c8 0.1 f p2?3 p2?2 p2?1 p2?4 agnd v ss v dd1 v dd c11 0.1 f c12 10 f c3 10 f c4 0.1 f c5 0.1 f c13 0.1 f c14 10 f c15 0.1 f c16 10 f + + + u2 adr01ar 4 5 2 6 j2 j1 7 4 3 2 6 v? v+ + + c9 10 f c10 0.1 f + tp1 r1 = 0 ad8065ar 8 10 4 5 6 1 2 3 7 9 j3 j4 j5 j6 lk2 lk1 a b figure 19. schematic of ad5426/ad5432/ad5443 evaluation board evaluation board for the ad5426/ad5432/ad5443 series of dacs the board consists of a 12-bit ad5443 and a current to voltage amplifier ad8065. included on the evaluation board is a 10 v reference adr01. an external reference may also be applied via an smb input. the evaluation kit consists of a cd-rom with self-installing pc software to control the dac. the software simply allows the user to write a code to the device. operating the evaluation board power supplies the board requires + + + ( ) ( ) f tantalum and 0.1 f ceramic capacitors. link1 (lk1) is provided to allow selection between the on-board reference (adr01) or an external reference applied through j2. for the ad5426/ad5432/ad5443 use link2 in the sdo position.
rev. 0 e20e ad5426/ad5432/ad5443 eval?ad5426/ ad5432/ad5443eb p1 p2 j2 j6 j5 j4 u1 u3 c11 u2 j3 vref vref j1 vout lk1 sdo/ldac sdo/ldac c10 c13 c14 c9 c1 r1 c2 c3 c6 c4 c16 c15 sync sync sdin sdin sclk sclk ldac lk2 sdo vdd vss vdd1 agnd tp1 c8 figure 20. silkscreen?component side view (top layer) c7 c12 figure 21. silkscreen?component side view (bottom layer)
rev. 0 ad5426/ad5432/ad5443 e21e overview of ad54xx devices part no. resolution no. dacs inl t s max interface package features ad5403 * 82 cs p cs p cs p cs p cs p cs p cs p cs p cs p cs p
rev. 0 e22e ad5426/ad5432/ad5443 outline dimensions 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.00 bsc 3.00 bsc 4.90 bsc pin 1 coplanarity 0.10 compliant to jedec standards mo-187ba
e23e
?4 d03162??/04(0)

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